Exposer Control with the pcIMAGE-SDIG

pcIMAGE-SDIG

The pcIMAGE-SDIG/AIAZ includes a timing generator which can create a signal on the EXPOSE output of the board.
It generates a rectangle signal with programmable cycle duration and symmetry with the function mvSetExpose().
The cycle duration corresponds to the line frequency and the low or high part gives the integration time
if the camera supports this integration control feature. Please note that on this mode the camera could not be
synchronized to the object movement. The camera is reseted by the board independent to the object speed.
The standard version of the SDIG doesn"t support the exposer control with an timing generator.

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